512k x 8 static ram cy7c1049bnv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06432 rev. ** revised february 1, 2006 features ?high speed ?t aa = 12 ns ? low active power ? 504 mw (max.) ? low cmos standby power (commercial l version) ? 1.8 mw (max.) ? 2.0v data retention (660 w at 2.0v retention) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features functional description [1] the cy7c1049bnv33 is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049bnv33 is available in a standard 400-mil-wide 36-pin soj and 44-pin tsopii packages with center power and ground (revolutionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 top view soj 12 13 33 36 35 34 16 15 21 22 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 5 i/o 4 a 9 a 0 i/o 0 i/o 1 i/o 2 oe a 17 a 16 a 13 ce a 9 a 18 18 17 19 20 gnd i/o 7 i/o3 i/o 6 v cc a 10 a 11 nc nc a 10 top view tsop we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 v ss a 17 a 2 ce i/o 0 a 3 a 4 18 17 20 19 i/o 1 27 28 25 26 22 21 23 24 v ss i/o 2 i/o 3 a 16 a 15 v cc oe i/o 7 i/o 6 i/o 5 i/o 4 a 14 a 13 a 12 a 11 a 9 a 10 nc nc nc nc nc nc nc a 18 nc nc nc
cy7c1049bnv33 document #: 001-06432 rev. ** page 2 of 8 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .....?0.5v to +4.6v dc voltage applied to outputs [2] in high z state .......................................?0.5v to v cc + 0.5v dc input voltage [2] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma selection guide -12 -15 -20 maximum access time (ns) 12 15 20 maximum operating current (ma) com?l 200 180 160 ind?l 220 200 170 maximum cmos standby current (ma) com?l/ind?l 8 8 8 com?l l0.5 0.5 0.5 operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 0.3v industrial ?40 c to +85 c dc electrical characteristics over the operating range parameter description test conditions -12 -15 -20 min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [2] ?0.5 0.8 ?0.5 0.8 ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc com?l 200 180 160 ma ind?l 220 200 170 ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 30 30 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l/ind?l 8 8 8 ma com?l l 0.5 0.5 0.5 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out i/o capacitance 8 pf notes: 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress application note, available on t he internet at www.cypress.com. 2. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 3. tested initially and after any design or process changes that may affect these parameters.
cy7c1049bnv33 document #: 001-06432 rev. ** page 3 of 8 ac test loads and waveforms ac switching characteristics [4] over the operating range -12 -15 -20 parameter description min.max.min.max.min.max.unit read cycle t power v cc (typical) to the first access [5] 111 s t rc read cycle time 12 15 20 ns t aa address to data valid 12 15 20 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 12 15 20 ns t doe oe low to data valid 6 7 8 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z [6, 7] 678ns t lzce ce low to low z [7] 333ns t hzce ce high to high z [6, 7] 678ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 12 15 20 ns write cycle [8, 9] t wc write cycle time 12 15 20 ns t sce ce low to write end 10 12 13 ns t aw address set-up to write end 10 12 13 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 101213ns t sd data set-up to write end 7 8 9 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [7] 333ns t hzwe we low to high z [6, 7] 678ns notes: 4. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. this part has a voltage regulator which steps down the voltage from 5v to 3.3v internally. t. power time has to be provided initially before a read/write operation is started. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 10. no input may exceed v cc + 0.5v 11. .t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 ns and slower speeds. 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope output (a) (b) r1 317 ? 167 ? r2 351 ? venin equivalent th 1.73v risetime:1 v/ns fall time: 1 v/ns
cy7c1049bnv33 document #: 001-06432 rev. ** page 4 of 8 data retention characteristics over the operating range (for l version only) parameter description conditions [10] min. max unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 330 a t cdr [3] chip deselect to data retention time 0ns t r [11] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current
cy7c1049bnv33 document #: 001-06432 rev. ** page 5 of 8 write cycle no. 1 (we controlled, oe high during write) [15, 16] write cycle no. 2 (we controlled, oe low) [16] truth table ce oe we i/o 0 ? i/o 7 mode power h x x high z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) notes: 15. data i/o is high-impedance if oe = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 17. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 17 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 17
cy7c1049bnv33 document #: 001-06432 rev. ** page 6 of 8 \\ ordering information speed (ns) ordering code package name package type operating range 12 cy7c1049bnv33-12zc 51-85087 44-pin tsop ii z44 commercial cy7c1049bnv33-12vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bnv33-12vi 51-85090 36- lead (400-mil) molded soj industrial cy7c1049bnv33-12vxi 51-85090 36-lead (400-mil) molded soj (pb-free) 15 cy7c1049bnv33-15vc 51-85090 36-lead (400-mil) molded soj commercial cy7c1049bnv33-15vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bnv33l-15vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bnv33-15zc 51-85087 44-pin tsop ii z44 cy7c1049bnv33-15vi 51-85090 36-lead (400-mil) molded soj industrial cy7c1049bnv33-15vxi 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bnv33-15zi 51-85087 44-pin tsop ii z44 20 cy7c1049bnv33-20vc 51-85090 36-lead (400-mil) molded soj commercial cy7c1049bnv33-20vxc 51-85090 36-lead (400-mil) molded soj (pb-free) cy7c1049bnv33-20vxi 51-85090 36-lead (400-mil) molded soj (pb-free) industrial please contact local sales representative regarding availability of these parts package diagrams 36-pin (400-mil) molded soj (51-85090) 51-85090-*b
cy7c1049bnv33 document #: 001-06432 rev. ** page 7 of 8 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 44-pin tsop ii z44 (51-85087) 51-85087-*a
cy7c1049bnv33 document #: 001-06432 rev. ** page 8 of 8 document history page document title: cy7c1049bnv33 512k x 8 static ram document number: 001-06432 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet
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